In general, average potential of video signals varies according to the information it contains, especially according to the brightness of the video signals. Therefore, a clamping circuit (described as a pedestal clamping circuit hereinafter) is generally provided in a semiconductor integrated circuit used for processing video signals, in order to keep a sink chip DC (DC indicates a direct current hereinafter) potential or a pedestal DC potential at a constant value.
This pedestal clamping circuit requires a clamping pulse synchronized to a timing of a pedestal signal to maintain a pedestal level at a constant DC potential. For a period when this clamping pulse is received in the pedestal clamping circuit, comparison is made between a pedestal DC potential of an input video signal and a DC potential of a clamping target (described as a reference potential hereinafter).
The difference obtained through the comparison is fed back, and the potential of the DC component of the video signal is adjusted according to the difference, by which the pedestal DC potential can be kept constant. Accordingly, when a timing of a clamping pulse is displaced from a timing of a pedestal signal, the pedestal signal can not be clamped to a desired DC potential.
FIG. 7 shows a simulated view of a pedestal clamping circuit based on the conventional technology. This pedestal clamping circuit comprises an input terminal 11 to which a video signal is inputted from an external device, a resistor 12 with one terminal thereof connected to the input terminal 11, a comparator 13 with a reversed input terminal thereof connected to the other terminal of the resistor 12, a constant voltage power unit 14 for loading a reference potential Vped to a non-reversed input terminal of the comparator 13, a pair of variable current sources 15, 16 connected to the other terminal the resistor 12 and an amount of current of each of which is controlled by output from the comparator 13, and a feedback capacitor 17 connected to an output terminal of the comparator 13.
A clamping pulse is inputted into the comparator 13 at a specified timing. Output from the pedestal clamping circuit can be obtained at the other edge of the resistor 12. The variable current source 15 is connected between the other edge of the resistor 12 and a positive supply voltage Vcc, while the variable current source 16 is connected between the other edge of the resistor 12 and a ground GND.
Effects due to the pedestal clamping circuit shown in FIG. 7 are explained. A video signal having been inputted from the input terminal 11 is then inputted to the reversed input terminal of the comparator 13 through the resistor 12. The video signal inputted into the comparator 13 consists of a pedestal signal to which a burst signal is superimposed as a reference for a color density or a color tone. The comparator 13 compares a potential of a video signal to the reference potential Vped during a period when a clamping pulse is received (e.g., a period when a clamping pulse is a relatively high potential level (described as a "H (high)" level hereinafter)), generates and outputs a feedback signal S1 according to the difference and outputs. The feedback signal S1 is fed back to the variable current sources 15, 16.
As a result of the feedback, when a potential of the video signal is lower than the reference potential Vped, current flows into the resistor 12 from the variable current source 15 which is at a higher potential so that the potential of the video signal is higher. On the contrary, when the potential of the video signal is higher than the reference potential Vped, current is drawn out from the resistor 12 by the variable current source 16 which is at a lower potential so that the potential of the video signal becomes lower. Thus, the resistor 12 and the variable current source 15 form a positive potential loading unit, while the resistor 12 and the variable current source 16 form a negative potential loading unit.
The capacitor 17 is charged or discharged according to an output from the comparator 13. This capacitor 17 maintains the charged state for a period when a clamping pulse is not received (e.g., a period when a clamping pulse is at a relatively low level (described as a "L (low)" level hereinafter)).
FIG. 8 shows a detail circuit configuration of the pedestal clamping circuit. This pedestal clamping circuit has an emitter-follower circuit 21 comprising an NPN transistor Tr1. A positive power voltage Vcc is applied to the collector of the NPN transistor Tr1 of this emitter-follower circuit 21, the emitter is branched and connected to one terminal of the resistor 12 and to the ground GND through another resistor 22, and a video signal is inputted into the base thereof.
This pedestal clamping circuit has a differential amplifier. The differential amplifier comprises a constant current source 23 connected to a power line with a positive power voltage Vcc applied thereto, a differential pair 24 of PNP transistors Tr2, Tr3 the emitters of each of which are connected to the constant current source 23, and a current mirror circuit 25 comprising a pair of NPN transistors Tr4, Tr5 connected to the differential pair 24 respectively. The differential pair 24 and current mirror circuit 25 correspond to the variable current source 15 and to the variable current source 16 shown in FIG. 7 respectively.
A specified bias potential is applied to the base of the PNP transistor Tr2 by a DC bias source 26. Inputted to the base of the PNP transistor Tr3 is an output from a circuit constituting a comparator described later. Collectors of the PNP transistors Tr2, Tr3 are connected to the collectors of the NPN transistors Tr4, Tr5.
The base terminals of the pair of NPN transistors Tr4, Tr5 are connected to the collector of the PNP transistor Tr3 in the side where output (namely a feedback signal S1) from a circuit constituting the comparator described later is inputted to the base thereof in the differential pair 24. Namely, in the NPN Transistor Tr5 connected to the side where output from the comparator described later of the current mirror circuit 25 is inputted to the base thereof, the base and the collector thereof are short-circuited. Each emitters of the pair of NPN transistors Tr4, Tr5 is connected to the ground GND.
The other terminal of the resistor 12 is connected to the output from the differential amplifier comprising the constant current source 23, differential pair 24 and current mirror circuit 25. In addition, the output from this differential amplifier is supplied to an external device, branched and inputted to a differential pair as one of circuits constituting the comparator described later.
The comparator comprises a current mirror circuit 27 comprising a pair of PNP transistors Tr6, Tr7 each having an emitter connected to the power line with a positive voltage Vcc loaded thereto; a differential pair 28 of NPN transistors Tr8, Tr9 connected to the current mirror circuit 27; and a constant current source 29 to which emitters of the NPN transistors Tr8, Tr9 constituting the differential pair 28 are connected through a switching element 30.
This comparator corresponds to the comparator 13 shown in FIG. 17. The output from this comparator is supplied to the base of the PNP transistor Tr3 constituting the differential pair 24 of the differential amplifier as described above, branched and supplied to the feedback capacitor 17. The other terminal of the constant current source 29 is connected to the ground GND.
The base terminals of the pair of PNP transistors Tr6, Tr7 are connected to the collector of the PNP transistor Tr7. Namely, in the PNP transistor Tr7 which is one of the two transistors constituting the current mirror circuit 27, the base and the collector are short-circuited. Each collectors of the PNP transistors Tr6, Tr7 are connected to the collectors of NPN transistors Tr8, Tr9 respectively.
A reference potential Vped is applied by the constant voltage power unit 14 shown in FIG. 7 to the base of the NPN transistor Tr9, connected to the line of the PNP transistor Tr7 with the base and collector short-circuited in the current mirror circuit 27. The base of the other NPN transistor Tr8 is connected to the other terminal of the resistor 12 as well as to the output terminal of the differential amplifier, and a video signal is inputted to the base terminal.
The switching element 30 whose opening and closing is controlled by the clamping pulse is provided. The switching element 30 is closed, for instance, when the clamping pulse is at the "H" level, and is opened when the clamping pulse is at the "L" level. Accordingly, only when the clamping pulse is at the "H" level, the comparator comprising the current mirror circuit 27, differential pair 28 and the constant current source 29 operates.
FIG. 9 shows a relation between the timing of a video signal and a clamping pulse. When the clamping pulse is ON, namely when it is at "H" level, the comparator comprising the current mirror circuit 27, differential pair 28 and the constant current source 29 compares the reference potential Vped supplied by the constant voltage power unit 14 to a pedestal potential of a video signal. The capacitor 17 charges or discharges according to the result of the comparison, and the result is maintained by the capacitor 17 when the clamping pulse is OFF, namely when it is at the "L" level. On the other hand, the differential amplifier comprising the constant current source 23, differential pair 24 and the current mirror circuit 25 controls a current passing through the resistor 12 according to the voltage maintained by the capacitor 17.
Thus, when a pedestal potential is higher than the reference potential Vped, the capacitor 17 is discharged and the voltage decreases. When input to the differential amplifier is lower than the reference potential (a specified bias potential applied by the DC bias source 26) of the differential amplifier, the current mirror circuit 25 works so that a current is drawn from the resistor 12. As a result, a pedestal DC potential at the output terminal decreases.
On the other hand, when the pedestal potential is lower than the reference potential Vped, the capacitor 17 is charged and the voltage increases. Then, when input to the differential amplifier is higher than the reference potential (a specified bias potential applied by the DC bias source 26) of the differential amplifier, the differential pair 24 works so that a current is supplied to the resistor 12. As a result, a pedestal DC potential at the output terminal increases. As a result of the feedback as described above, the pedestal potential of the video signal to be outputted is equal to the reference potential Vped.
Clamping circuits are disclosed, for instance, in Japanese Patent Laid-Open Publication No. HEI 8-98057, Japanese Patent Laid-Open Publication No. HEI 8-195894 and Japanese Patent Laid-Open Publication No. HEI 3-226074.
In a case of an actual complex video signal, a burst signal exists in a front porch section thereof. The burst signal occupies, as shown in FIG. 9, most of the pedestal section in the complex video signal and it is extremely difficult to set a clamping pulse in portion where the burst signal is absent. Accordingly, a burst signal exists in the clamping period set by a clamping pulse. A frequency of the burst signal is around 3.58 MHz (or around 4.43 MHz), and a comparator generally reacts to a signal at this frequency.
Accordingly, in the pedestal clamping circuit shown in FIG. 7 and FIG. 8, as a result of comparison between the reference potential Vped and a potential of a video signal in a comparator, an AC component derived from the burst signal is outputted together with a feedback DC voltage to a terminal of the feedback capacitor, as shown in FIG. 10, as a result of which the comparator tries to convert the burst signal to a DC current. Hence, the burst signal in the output video signal is attenuated as compared to that in the input video signal, which results in the fact that the burst signal is damaged. Further, phase of the burst signal may be changed.
Although this drawback can be overcome by using a feedback capacitor having a larger capacitance, the clamping speed becomes extremely slow, and this is not practical.
Also, there is found no consideration on a burst signal included in a video signal in the clamping circuits disclosed in Japanese Patent Laid-Open Publication No. HEI 8-98057, HEI 8-195894 and HEI 3-226074, so that, when a burst signal is superimposed on a pedestal signal, it is not clear whether the pedestal potential can be clamped to a specified reference potential without any damage to the burst signal or not.